The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Feb. 17, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Rakesh Balakrishnan, Bangalore, IN;

Eldhose Peter, Bangalore, IN;

Akhilesh Yadav, Bangalore, IN;

Ramanathan Muthiah, Bangalore, IN;

Vimal Kumar Jain, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1027 (2016.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 25/065 (2023.01); G06F 13/16 (2006.01); G06F 12/02 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G06F 12/0246 (2013.01); G06F 13/1684 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 25/0657 (2013.01); G06F 2212/7201 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); H01L 2225/06541 (2013.01); H10B 41/27 (2023.02);
Abstract

A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller receives commands from a host, performs logical address to physical address translation ('address translation') operations for the commands, and instructs the integrated memory assembly to perform one or more operations in support of the command. The control die also includes the ability to perform the address translation. When performing a command from the host, the memory controller can choose to perform the necessary address translation or instruct the control die to perform the address translation. When the control die performs the address translation, the resulting physical address is used by the control die to perform one or more operations in support of the command.


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