The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Mar. 15, 2022
Applicant:

Realtek Semiconductor Corp., HsinChu, TW;

Inventors:

Chao-Min Lai, HsinChu, TW;

Han-Chieh Hsieh, HsinChu, TW;

Tang-Hung Chang, HsinChu, TW;

Hung-Wei Wang, HsinChu, TW;

Chun-Yi Kuo, HsinChu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 19/00 (2006.01); H03K 19/17784 (2020.01);
U.S. Cl.
CPC ...
H03K 19/01855 (2013.01); H03K 19/0016 (2013.01); H03K 19/17784 (2013.01);
Abstract

The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.


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