The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Apr. 07, 2022
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, KR;

Inventors:

Ju Hyoung Park, Suwon-si, KR;

Young Sik Hur, Suwon-si, KR;

Sung Yong An, Suwon-si, KR;

Myeong Woo Han, Suwon-si, KR;

Kyu Bum Han, Suwon-si, KR;

Dae Ki Lim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 1/22 (2006.01); H01Q 21/06 (2006.01);
U.S. Cl.
CPC ...
H01Q 21/065 (2013.01); H01Q 1/2283 (2013.01);
Abstract

A chip antenna module array includes a first chip antenna module including: a first solder layer disposed below a first dielectric layer; a first feed via disposed in the first dielectric layer; a first patch antenna pattern disposed above the first dielectric layer and having a first resonant frequency; and a first coupling pattern spaced apart from the first patch antenna pattern, and not vertically overlapping the first patch antenna pattern. The chip antenna module array includes a second chip antenna module including: a second solder layer disposed below a second dielectric layer; a second feed via disposed in the second dielectric layer; a second patch antenna pattern disposed above the second dielectric layer and having a second resonant frequency; and a second coupling pattern disposed above and vertically overlapping the second patch antenna pattern. The first and second chip antenna modules are disposed spaced apart on a connection member.


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