The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Mar. 02, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Shinya Naito, Toyota Aichi, JP;

Keiji Hosotani, Yokkaichi Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H01L 29/423 (2006.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 29/792 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/788 (2013.01); H01L 29/792 (2013.01);
Abstract

A semiconductor device includes first and second gate electrodes, a semiconductor layer between the first and second gate electrodes and extending along a first direction, a first gate insulating layer between the first gate electrode and the semiconductor layer, a second gate insulating layer between the second gate electrode and the semiconductor layer, a first insulating layer including a first region adjacent to the first gate electrode in the first direction and contacting the semiconductor layer, and a second insulating layer extending including a second region adjacent to the second gate electrode in the first direction and contacting the semiconductor layer. An interface between the first region and the semiconductor layer in a direction crossing the first direction is adjacent to the first gate electrode in the first direction.


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