The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Dec. 02, 2020
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventors:

Julio C. Costa, Oak Ridge, NC (US);

Mickael Renault, San Jose, CA (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 24/20 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/4871 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/3672 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/66 (2013.01); H01L 24/19 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01);
Abstract

The present disclosure relates to a radio frequency (RF) device and a process for making the same. According to the process, a precursor wafer, which includes device regions, individual interfacial layers, individual p-type doped layers, and a silicon handle substrate, is firstly provided. Each individual interfacial layer is over an active layer of a corresponding device region, each individual p-type doped layer is over a corresponding individual interfacial layer, and the silicon handle substrate is over each individual p-type doped layer. Herein, each individual interfacial layer is formed of SiGe, and each individual p-type doped layer is a silicon layer doped with a p-type material that has a doped concentration greater than 1E18cm-3. Next, the silicon handle substrate is completely removed to provide an etched wafer, and each individual p-type doped layer is completely removed from the etched wafer.


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