The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Sep. 07, 2021
Applicant:

Shenzhen Goodix Technology Co., Ltd., Shenzhen, CN;

Inventors:

Jianfeng Xue, Shenzhen, CN;

Yunning Li, Shenzhen, CN;

Yuan Su, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); G01J 1/46 (2006.01); G06F 21/75 (2013.01); G06F 21/72 (2013.01); H01L 23/552 (2006.01); G01J 1/44 (2006.01); G01J 1/42 (2006.01); H01L 27/144 (2006.01);
U.S. Cl.
CPC ...
H01L 23/576 (2013.01); G01J 1/4257 (2013.01); G01J 1/46 (2013.01); G06F 21/72 (2013.01); G06F 21/75 (2013.01); G06F 21/755 (2017.08); H01L 23/552 (2013.01); G01J 2001/446 (2013.01); H01L 27/1443 (2013.01);
Abstract

Embodiments of the present disclosure provide a detection circuit for a laser fault injection attack on a chip and a security chip. The detection circuit includes a first capacitor, a second capacitor, a first switch, a second switch, a photosensitive element, a first NMOS transistor, and a second NMOS transistor. A drain of the first NMOS transistor is configured to output a first voltage signal, and a drain of the second NMOS transistor is configured to output a second voltage signal. The first voltage signal and the second voltage signal are configured to indicate that the chip is attacked by laser fault injection, thereby realizing detection of the laser fault injection attack, and ensuring the robustness and security of the chips.


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