The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2023
Filed:
Oct. 23, 2020
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Dong Hyuk Kim, Icheon-si, KR;
Sung Lae Oh, Icheon-si, KR;
Tae Sung Park, Icheon-si, KR;
Soo Nam Jung, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 27/11573 (2017.01); G11C 7/18 (2006.01); H01L 23/522 (2006.01); H01L 23/535 (2006.01); H01L 27/11529 (2017.01); H01L 27/11578 (2017.01); H01L 27/11551 (2017.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); G11C 7/18 (2013.01); H01L 23/5226 (2013.01); H01L 23/535 (2013.01); H01L 27/11529 (2013.01); H01L 27/11551 (2013.01); H01L 27/11573 (2013.01); H01L 27/11578 (2013.01);
Abstract
A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes a first connection pattern, a bit line disposed over the first connection pattern in a vertical direction, and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern so that the bit-line contact pad, and formed as an island when viewed along the vertical direction.