The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Dec. 02, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Young Jun Park, Gyeonggi-do, KR;

Young Jun Ku, Gyeonggi-do, KR;

In Keun Kim, Gyeonggi-do, KR;

Sang Sic Yoon, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/54 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 29/54 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/222 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01);
Abstract

A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.


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