The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Apr. 28, 2021
Applicant:

Flc Technology Group, Inc., Santa Clara, CA (US);

Inventors:

Xiaojue Zeng, Santa Clara, CA (US);

Cheng Chung Wang, Fremont, CA (US);

Fan Yang, San Jose, CA (US);

Rong Xu, Mountain View, CA (US);

Bo Hu, Santa Clara, CA (US);

Hunglin Hsu, Cupertino, CA (US);

Sehat Sutardja, Las Vegas, NV (US);

Assignee:

FLC Technology Group, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1064 (2013.01); G06F 11/1068 (2013.01); G06F 11/3037 (2013.01); G06F 12/0238 (2013.01); G06F 13/1668 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/403 (2013.01);
Abstract

A system and method for caching memory request verification data comprising a memory request generator configured to generate a memory request designating requested data and memory request verification data. A bus is configured to carry the memory request from the memory request generator to a cache memory that stores verification data, and upon receiving the memory request is configured to: retrieve stored verification data from the cache memory, compare the stored verification data to the memory request verification data, and responsive to a match between the stored verification data to the memory request verification data, designate a memory request validation. Also part of the system is a memory controller configured to, responsive to a memory request validation, retrieve data specified in the memory request from a main memory and provide the data to the memory request generator over the bus. A main memory configured to store the requested data.


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