The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Jun. 03, 2019
Applicant:

Sciosense B.v., AE Eindhoven, NL;

Inventor:

Fridolin Michel, Rapperswil, CH;

Assignee:

SCIOSENSE B.V., AE Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01K 7/01 (2006.01); H03M 1/06 (2006.01); H03M 1/08 (2006.01);
U.S. Cl.
CPC ...
G01K 7/01 (2013.01); H03M 1/0607 (2013.01); H03M 1/089 (2013.01);
Abstract

In an embodiment a semiconductor device includes a first diode and a second diode of specified sizing or biasing ratio, a negative voltage supply, a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor, an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array, and wherein the second diode is connected between the negative supply voltage and a second input of the array and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array and a second node present between the second diode and the second input of the array.


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