The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Jun. 11, 2021
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Boon Teik Chan, Wilsele, BE;

Ruoyu Li, Leuven, BE;

Stefan Kubicek, Pellenberg, BE;

Julien Jussot, Kessel-Lo, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 60/01 (2023.01); H10N 60/10 (2023.01); H10N 60/83 (2023.01); H10N 69/00 (2023.01);
U.S. Cl.
CPC ...
H10N 60/01 (2023.02); H10N 60/11 (2023.02); H10N 60/128 (2023.02); H10N 60/83 (2023.02); H10N 69/00 (2023.02);
Abstract

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.


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