The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Jun. 12, 2019
Applicant:

Fujikura Ltd., Tokyo, JP;

Inventors:

Masakazu Sato, Sakura, JP;

Nobuki Ueta, Sakura, JP;

Yoshio Nakao, Sakura, JP;

Masatoshi Inaba, Sakura, JP;

Assignee:

Fujikura Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/40 (2006.01);
U.S. Cl.
CPC ...
H05K 1/116 (2013.01); H05K 1/185 (2013.01); H05K 3/0026 (2013.01); H05K 3/4053 (2013.01); H05K 2201/09563 (2013.01); H05K 2201/09854 (2013.01);
Abstract

A component-embedded substrate includes: insulating layers each including a wiring pattern; an embedded component including a connection terminal; a plurality of vias that electrically connect the connection terminal to the wiring patterns adjacent to each other in a lamination direction. Each of the vias is composed of a via hole in the insulating layer and a conductive material in the via hole. One of the vias is a connection via connected to the connection terminal, and another of the vias is an adjacent via adjacent to the connection via in the lamination direction. The connection via and adjacent via overlap in a plan view. S1/A1≤0.61 and S1/A2≤0.61 are satisfied, where A1 is an average cross-sectional area of the connection via, A2 is an average cross-sectional area of the adjacent via, and S1 is an overlapping area of the connection via and adjacent via in the plan view.


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