The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

May. 23, 2022
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Zhihong Huang, Milpitas, CA (US);

Di Liang, Santa Barbara, CA (US);

Yuan Yuan, Milpitas, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 29/861 (2006.01); H01L 31/105 (2006.01); H01L 31/028 (2006.01); H04B 10/66 (2013.01); H01L 27/144 (2006.01); H01L 31/18 (2006.01); H04J 14/02 (2006.01);
U.S. Cl.
CPC ...
H01L 31/105 (2013.01); H01L 27/1446 (2013.01); H01L 31/028 (2013.01); H01L 31/1804 (2013.01); H04B 10/66 (2013.01); H04J 14/02 (2013.01);
Abstract

A device may include: a highly doped nSi region; an intrinsic silicon multiplication region disposed on at least a portion of the nSi region, the intrinsic silicon multiplication having a thickness of about 90-110 nm; a highly doped pSi charge region disposed on at least part of the intrinsic silicon multiplication region, the pSi charge region having a thickness of about 40-60 nm; and a pGe absorption region disposed on at least a portion of the pSi charge region; wherein the pGe absorption region is doped across its entire thickness. The thickness of the nSi region may be about 100 nm and the thickness of the pSi charge region may be aboutnm. The pGe absorption region may confine the electric field to the multiplication region and the charge region to achieve a temperature stability of 4.2 mV/°C.


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