The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Aug. 03, 2020
Applicant:

Sunpower Corporation, San Jose, CA (US);

Inventors:

Peter J. Cousins, Los Altos, CA (US);

David D. Smith, Campbell, CA (US);

Seung Bum Rim, Palo Alto, CA (US);

Assignee:

Maxeon Solar Pte. Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0747 (2012.01); H01L 31/0216 (2014.01); H01L 31/068 (2012.01); H01L 31/18 (2006.01); H01L 31/0236 (2006.01); H01L 31/0368 (2006.01); H01L 31/0224 (2006.01); H01L 31/20 (2006.01);
U.S. Cl.
CPC ...
H01L 31/0747 (2013.01); H01L 31/02167 (2013.01); H01L 31/02168 (2013.01); H01L 31/02363 (2013.01); H01L 31/022425 (2013.01); H01L 31/022433 (2013.01); H01L 31/03682 (2013.01); H01L 31/0682 (2013.01); H01L 31/182 (2013.01); H01L 31/1804 (2013.01); H01L 31/202 (2013.01); Y02E 10/52 (2013.01); Y02E 10/546 (2013.01); Y02E 10/547 (2013.01); Y02P 70/50 (2015.11);
Abstract

A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.


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