The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Nov. 13, 2019
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yingwei Liu, Beijing, CN;

Qi Yao, Beijing, CN;

Ke Wang, Beijing, CN;

Zhanfeng Cao, Beijing, CN;

Zhiwei Liang, Beijing, CN;

Muxin Di, Beijing, CN;

Guangcai Yuan, Beijing, CN;

Xue Jiang, Beijing, CN;

Dongni Liu, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H01L 51/56 (2006.01); H01L 51/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3276 (2013.01); H01L 27/326 (2013.01); H01L 51/0097 (2013.01); H01L 51/56 (2013.01); H01L 2227/323 (2013.01); H01L 2251/305 (2013.01); H01L 2251/5338 (2013.01);
Abstract

The present disclosure relates to a method of manufacturing an array substrate. The method of manufacturing an array substrate may include forming a main via hole in a substrate, filling a first conductive material in the main via hole, and forming a pixel circuit layer on a first surface of the substrate. The pixel circuit layer may include a first via hole. An orthographic projection of the first via hole on the substrate may at least partially overlap the corresponding main via hole.


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