The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2023
Filed:
Mar. 31, 2021
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Rafael Jose Lizares Guevara, Metro Manila, PH;
John Carlo Cruz Molina, Bataan, PH;
Steffany Ann Lacierda Moreno, Tarlac, PH;
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 21/4828 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 2224/13019 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16258 (2013.01); H01L 2224/81024 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/17747 (2013.01);
Abstract
In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.