The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2023
Filed:
May. 06, 2021
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Hyun Seung Kim, Icheon-si, KR;
Hyeong Soo Jeong, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/14 (2006.01); G11C 29/10 (2006.01); G11C 29/44 (2006.01); G11C 29/56 (2006.01); G11C 7/10 (2006.01); G11C 8/18 (2006.01); G11C 29/36 (2006.01);
U.S. Cl.
CPC ...
G11C 29/14 (2013.01); G11C 7/1012 (2013.01); G11C 7/1057 (2013.01); G11C 7/1063 (2013.01); G11C 8/18 (2013.01); G11C 29/10 (2013.01); G11C 29/44 (2013.01); G11C 29/56 (2013.01); G11C 2029/3602 (2013.01);
Abstract
A memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data.