The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Jun. 30, 2020
Applicant:

Nuvoton Technology Corporation, Hsin-chu, TW;

Inventors:

Ziv Hershman, Givat Shmuel, IL;

Yoel Hayon, Givatayim, IL;

Moshe Alon, Tel-Aviv, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G11C 29/02 (2006.01); G11C 29/44 (2006.01); G11C 29/38 (2006.01); G11C 29/50 (2006.01); G06F 21/57 (2013.01); G11C 5/14 (2006.01); G06F 30/34 (2020.01); G06F 1/025 (2006.01); G06F 3/06 (2006.01); G06F 21/78 (2013.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/12005 (2013.01); G06F 21/57 (2013.01); G11C 5/143 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/12015 (2013.01); G11C 29/38 (2013.01); G11C 29/44 (2013.01); G11C 29/50004 (2013.01); G06F 1/025 (2013.01); G06F 3/062 (2013.01); G06F 21/78 (2013.01); G06F 30/34 (2020.01); G11C 2029/0407 (2013.01);
Abstract

An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.


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