The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Aug. 27, 2020
Applicant:

Mentor Graphics Corporation, Wilsonville, OR (US);

Inventors:

Xijiang Lin, West Linn, OR (US);

Wu-Tung Cheng, Lake Oswego, OR (US);

Takeo Kobayashi, Beaverton, OR (US);

Andreas Glowatz, Heidenau, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31724 (2013.01); G01R 31/3177 (2013.01);
Abstract

This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.


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