Calibration of timing skews in a multi-channel interleaved analog- to-digital converter (adc) by auto-correlation of muxed-together channels in binary output tree

Abstract

An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. An auto-correlator generates a sign of a correlation error for a pair of ADC digital outputs. SAR bits are tested with the correlation sign bit determining when to add or subtract SAR bits. First all pairs are calibrated in a first level of a binary tree of mux-correlators. Then skews between remote pairs and groups are calibrated in upper levels of the binary tree using auto-correlators with inputs muxed from groups of ADC outputs input to the binary tree of mux-correlators. The binary tree of mux-correlators can include bypasses for odd and non-binary values of N. Sampling clock and component timing skews are reduced to one LSB among both adjacent channels and remote channels.