The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2023
Filed:
Oct. 01, 2021
Applicant:
Psemi Corporation, San Diego, CA (US);
Inventors:
Ravindranath D. Shrivastava, San Diego, CA (US);
Alper Genc, San Diego, CA (US);
Assignee:
PSEMI CORPORATION, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H03K 17/041 (2006.01); H03K 17/0412 (2006.01); H03K 17/693 (2006.01); H04B 1/44 (2006.01); H03K 17/687 (2006.01); H03K 17/06 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H03K 17/687 (2013.01); H03K 17/063 (2013.01); H01L 27/0629 (2013.01);
Abstract
A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.