The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2023

Filed:

Dec. 09, 2020
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Yoshihiro Sato, Osaka, JP;

Junji Hirase, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H04N 5/359 (2011.01); H01L 27/30 (2006.01); H04N 5/369 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14603 (2013.01); H01L 27/1461 (2013.01); H01L 27/1463 (2013.01); H01L 27/14609 (2013.01); H01L 27/14612 (2013.01); H01L 27/14614 (2013.01); H01L 27/14616 (2013.01); H01L 27/14636 (2013.01); H01L 27/14638 (2013.01); H01L 27/307 (2013.01); H04N 5/359 (2013.01); H04N 5/379 (2018.08);
Abstract

An imaging device including: a photoelectric converter that generates a signal charge by photoelectric conversion of light; a semiconductor substrate; a charge accumulation region that is an impurity region of a first conductivity type in the semiconductor substrate, the charge accumulation region being configured to receive the signal charge; a first transistor that includes, as a source or a drain, a first impurity region of the first conductivity type in the semiconductor substrate; and a blocking structure that is located between the charge accumulation region and the first transistor. The blocking structure includes a second impurity region of a second conductivity type in the semiconductor substrate, the second conductivity type being different from the first conductivity type, and a first electrode that is located above the semiconductor substrate, the first electrode being configured to be applied with a first voltage.


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