The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2023

Filed:

Jan. 23, 2020
Applicant:

Lumileds Llc, San Jose, CA (US);

Inventors:

Tze Yang Hin, Cupertino, CA (US);

Anantharaman Vaidyanathan, San Jose, CA (US);

Srini Banna, San Jose, CA (US);

Ronald Johannes Bonne, Plainfield, IL (US);

Assignee:

Lumileds LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); F21V 23/00 (2015.01); H01L 33/62 (2010.01); F21S 41/153 (2018.01); H01L 27/15 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2023.01); F21Y 105/10 (2016.01); F21Y 115/10 (2016.01); F21Y 105/16 (2016.01);
U.S. Cl.
CPC ...
H01L 21/4853 (2013.01); F21S 41/153 (2018.01); F21V 23/002 (2013.01); H01L 21/486 (2013.01); H01L 21/6835 (2013.01); H01L 24/19 (2013.01); H01L 24/81 (2013.01); H01L 24/82 (2013.01); H01L 25/167 (2013.01); H01L 27/156 (2013.01); H01L 33/62 (2013.01); F21Y 2105/10 (2016.08); F21Y 2105/16 (2016.08); F21Y 2115/10 (2016.08); H01L 2221/68345 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/24225 (2013.01); H01L 2224/8112 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/82815 (2013.01); H01L 2924/12041 (2013.01); H01L 2933/0041 (2013.01); H01L 2933/0066 (2013.01);
Abstract

Methods of manufacturing a system are described. A method includes attaching a silicon backplane to a carrier and molding the silicon backplane on the carrier such that a molding material surrounds side surfaces of the silicon backplane to form a structure comprising a substrate with an embedded silicon backplane. The structure has a first surface opposite the carrier, a second surface adjacent the carrier, and side surfaces. At least one via is formed through the molding material and filled with a metal material. A metal layer is formed on a central region of the first surface of the structure. Redistribution layers are formed on the first surface of the structure adjacent the metal layer.


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