The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2023

Filed:

May. 07, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Andreas Jansen, Murnau, DE;

Richard Heinz, Munich, DE;

Catalina-Petruta Juglan, Botosani, RO;

Stephan Leisenheimer, Deisenhofen, DE;

Lacramioara Mihaela Smochina, Roman, RO;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 13/374 (2006.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01);
U.S. Cl.
CPC ...
G06F 13/4282 (2013.01); G06F 9/30101 (2013.01); G06F 9/321 (2013.01); G06F 13/374 (2013.01); G06F 13/4022 (2013.01);
Abstract

A serial peripheral interface (SPI) communication system includes a memory configured with a start register address and an end register address that define a register address range for a data operation; a chip select terminal configured to receive a chip select signal comprising an active and idle signal levels that define a plurality of chip select frames; a serial data input terminal configured to receive a master out, slave in (MOSI) signal, wherein the MOSI signal includes configuration information received in a first chip select frame of the data operation, wherein the configuration information includes an operation command bit indicating whether the data operation is a write operation or a read out operation and an auto-incrementation control bit indicating whether automatic register address incrementation across chip select frames is enabled or disabled; and a serial data output terminal configured to transmit a master in, slave out (MISO) signal.


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