The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2023

Filed:

Aug. 19, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Wai Hung Tsang, Markham, CA;

Prithayan Barua, Atlanta, GA (US);

Ettore Tiotto, Whitby, CA;

Bardia Mahjour, Newmarket, CA;

Jun Shirako, Atlanta, GA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 8/41 (2018.01); G06F 12/0864 (2016.01);
U.S. Cl.
CPC ...
G06F 8/4442 (2013.01); G06F 12/0864 (2013.01); G06F 2212/1021 (2013.01);
Abstract

Aspects include modeling data cache utilization for each loop in a loop nest; estimating total data cache lines fetched in one iteration of the loop; and determining the possibility of data cache reuse across loop iterations using data cache lines fetched and associativity constraints. Aspects also include estimating, for memory reference pairs, reuse by one reference of data cache line fetched by another; estimating total number of cache misses for all iterations of the loop; and estimating total number of cache misses of a reference for iterations of a next outer loop as equal to total cache misses for an entire inner loop. Aspects further include estimating memory cost of a loop unroll and jam transformation, without performing the transformation; and extending a data cache model to estimate best unroll-and-jam factors for the loop nest, capable of minimizing total cache misses incurred by the memory references in the loop body.


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