The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2023

Filed:

Nov. 01, 2021
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Kohichi Nakamura, Kanagawa, JP;

Hiroaki Kameyama, Kanagawa, JP;

Koichiro Iwata, Kanagawa, JP;

Yu Arishima, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/374 (2011.01); H04N 5/376 (2011.01); H04N 5/378 (2011.01); H03M 1/00 (2006.01); H03M 1/56 (2006.01); H03M 1/12 (2006.01); H03M 1/82 (2006.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H04N 5/37455 (2013.01); H03M 1/123 (2013.01); H03M 1/56 (2013.01); H04N 5/3765 (2013.01);
Abstract

An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.


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