The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2023

Filed:

Sep. 22, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jianwen Ye, Apex, NC (US);

Bo Sun, Carlsbad, CA (US);

Cheng Zhong, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/01 (2006.01); H03K 19/20 (2006.01); H03L 7/081 (2006.01); H03K 5/00 (2006.01); H04B 1/40 (2015.01); H04L 12/40 (2006.01);
U.S. Cl.
CPC ...
H03K 5/00006 (2013.01); H03K 5/01 (2013.01); H03K 19/20 (2013.01); H03L 7/0812 (2013.01); H04B 1/40 (2013.01); H04L 12/40052 (2013.01); H03K 2005/00013 (2013.01);
Abstract

A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.


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