The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2023
Filed:
Mar. 09, 2021
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventor:
Seok Cheon Baek, Anyang-si, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 29/10 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 27/11565 (2017.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/1037 (2013.01);
Abstract
A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.