The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2023

Filed:

Jun. 28, 2021
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Thomas C. Fowler, Georgetown, TX (US);

Jerome T. Wenske, Cedar Creek, TX (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/71 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5225 (2013.01); H01L 21/71 (2013.01); H01L 28/40 (2013.01); H01L 24/05 (2013.01); H01L 2224/04042 (2013.01);
Abstract

An integrated circuit includes a capacitor with a bottom conductive plate and a top conductive plate. A passivation layer is disposed above the top conductive plate. An intermetal dielectric layer is disposed between the bottom conductive plate and the top conductive plate and is formed of a first dielectric material. Shield layers are disposed between the top conductive plate and above the intermetal dielectric layer and extend horizontally to at least past guard rings. The shield layers include a dielectric layer formed of dielectric material having a dielectric constant greater than the material of the intermetal dielectric layer. The shield layers include horizontally offset trenches to stop horizontal flow of current in the shield layers. The offset ensures there is no vertical path from the passivation layer to lower/ground potentials through the shield layers.


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