The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2023

Filed:

Apr. 28, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Takashi Nakagawa, Kanagawa, JP;

Takayuki Ikeda, Kanagawa, JP;

Hidetomo Kobayashi, Kanagawa, JP;

Hideaki Shishido, Kanagawa, JP;

Shuichi Katsui, Kanagawa, JP;

Kiyotaka Kimura, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G09G 2300/0814 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01); H01L 27/1225 (2013.01); H01L 29/7869 (2013.01);
Abstract

A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.


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