Process and hardware implementation of adaptive real-time neural spike sorting

Abstract

Various methods and embodiments of the present technology generally relate to neural spike sorting in real-time. More specifically, some embodiments relate to a real-time neural spike sorting process using distributed nodes and edges to form clusters in the vector space to learn the neural spike data distribution adaptively for neural spike classification in real-time. The state of the brain or the onset of a neurological disorder can be determined by analyzing the neural spike firing pattern, and the first stage of the neural data analysis is to sort the recorded neural spikes to their originating neurons. Methods that can sort the recorded neural spikes in real-time with low system latency and can be implemented with resource limited digital electronic hardware, including a Field-Programming Gate Array (FPGA), an Application-Specific Integrated Circuit and an embedded microprocessor, are beneficial in understanding neuronal networks and controlling neurological disorders.