The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2023
Filed:
Nov. 16, 2020
Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof
Sandisk Technologies Llc, Addison, TX (US);
Monica Titus, Sunnyvale, CA (US);
Zhixin Cui, Yokkaichi, JP;
Senaka Kanakamedala, San Jose, CA (US);
Yao-Sheng Lee, Tampa, FL (US);
Chih-Yu Lee, Yokkaichi, JP;
SANDISK TECHNOLOGIES LLC, Addison, TX (US);
Abstract
A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.