The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Mar. 02, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Liang Li, Shanghai, CN;

Jenny Qin, Shanghai, CN;

Minna Li, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 29/10 (2006.01); H01L 21/66 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); H01L 22/20 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/0217 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80125 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/80908 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06593 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

Alignment of a first wafer bonded to a second wafer can be determined using electrical wafer alignment methods. A wafer stack can be formed by overlaying a second wafer over a first wafer such that second metal bonding pads of the second wafer contact first metal bonding pads of the first wafer. A leakage current or a capacitance measurement step is performed between first alignment diagnostic structures in the first wafer and second alignment diagnostic structures in the second wafer for multiple mating pairs of first semiconductor dies in the first wafer and second semiconductor dies in the second wafer to determine the alignment.


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