The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Jan. 29, 2021
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventor:

Naoko Kodama, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02063 (2013.01); H01L 21/265 (2013.01); H01L 21/31144 (2013.01); H01L 29/0696 (2013.01); H01L 29/66325 (2013.01);
Abstract

A method of manufacturing a semiconductor device, including preparing a semiconductor wafer having first and second main surfaces opposite to each other, forming a photoresist film on the first main surface of the semiconductor wafer, forming a plurality of openings at predetermined positions in the photoresist film, cleaning the semiconductor wafer with water after the openings are formed, drying the semiconductor wafer by rotating the semiconductor wafer around a center axis that is orthogonal to the first main surface of the semiconductor wafer, to thereby generate a centrifugal force to cause the water that is left in the openings of the photoresist film to fly off the semiconductor wafer, and ion-implanting a predetermined impurity by a predetermined acceleration energy from the first main surface of the semiconductor wafer, using the photoresist film as a mask, after the drying. The drying process includes setting a rotational speed of the semiconductor wafer to be at most an upper limit value.


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