The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Oct. 17, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Aaron Ng, San Jose, CA (US);

Elliott Delaye, San Jose, CA (US);

Ehsan Ghasemi, San Jose, CA (US);

Xiao Teng, Cupertino, CA (US);

Jindrich Zejda, Saratoga, CA (US);

Yongjun Wu, Cupertino, CA (US);

Sean Settle, San Jose, CA (US);

Ashish Sirasao, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/04 (2006.01); G06N 3/08 (2006.01); G06N 3/063 (2006.01);
U.S. Cl.
CPC ...
G06N 3/04 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01);
Abstract

In the disclosed methods and systems for processing in a neural network system, a host computer system writes a plurality of weight matrices associated with a plurality of layers of a neural network to a memory shared with a neural network accelerator. The host computer system further assembles a plurality of per-layer instructions into an instruction package. Each per-layer instruction specifies processing of a respective layer of the plurality of layers of the neural network, and respective offsets of weight matrices in a shared memory. The host computer system writes input data and the instruction package to the shared memory. The neural network accelerator reads the instruction package from the shared memory and processes the plurality of per-layer instructions of the instruction package.


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