The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Oct. 18, 2021
Applicant:

Mellanox Technologies, Ltd., Yokneam, IL;

Inventors:

Tzahi Oved, Ramat Gan, IL;

Achiad Shochat, Rosh Pina, IL;

Liran Liss, Atzmon, IL;

Noam Bloch, Bat Shlomo, IL;

Aviv Heller, Rishon LeZion, IL;

Idan Burstein, Akko, IL;

Ariel Shahar, Jerusalem, IL;

Peter Paneah, Nesher, IL;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 2213/28 (2013.01);
Abstract

Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.


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