The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Mar. 27, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Andrew D. Baptist, Mt. Pleasant, WI (US);

Yogesh R. Vedpathak, Chicago, IL (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/1072 (2016.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 12/1081 (2016.01); G06F 12/109 (2016.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 3/061 (2013.01); G06F 3/067 (2013.01); G06F 3/0659 (2013.01); G06F 11/1076 (2013.01); G06F 12/1072 (2013.01); G06F 12/109 (2013.01); G06F 12/1081 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/154 (2013.01); G06F 2212/263 (2013.01);
Abstract

A method begins by a storage unit of a dispersed storage network (DSN) receiving access requests which include a logical DSN address and a storage function. The method continues with a first processing module of the storage unit performing logical to physical address conversions of logical DSN addresses of the access requests to physical addresses of a plurality of main memories. For a first access request of the access requests, the method continues with the first processing module identifying a first main memory based on the physical address resulting from the physical address conversion. The method continues with the first processing module identifying a first processing thread of a plurality of processing threads based on allocation of the plurality of processing threads to the plurality of main memories. The method continues with the first processing thread executing tasks of the first access request to fulfill the first access request.


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