The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Dec. 03, 2020
Applicant:

Renesas Electronics America Inc., Milpitas, CA (US);

Inventors:

Yang Li, Fremont, CA (US);

Sungkeun Lim, Cary, NC (US);

Zhigang Liang, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/003 (2006.01); H02J 7/00 (2006.01); H03K 5/26 (2006.01); H02M 1/00 (2006.01); H02M 3/156 (2006.01); H02J 1/00 (2006.01);
U.S. Cl.
CPC ...
H02J 7/00712 (2020.01); H02M 1/0016 (2021.05); H02M 3/1566 (2021.05); H03K 5/003 (2013.01); H03K 5/26 (2013.01); H02J 1/001 (2020.01); H02J 7/007 (2013.01);
Abstract

Example implementations include a method of obtaining an input voltage of a power converter circuit and a system voltage of the power converter circuit, obtaining a voltage rate gain based on an aggregate inductance of the power converter circuit, and in accordance with a determination that the input voltage and the system voltage are not equal, generating a rate offset voltage based on the voltage rate gain and the system voltage difference. Example implementations also include a device with a rate predictor device operatively coupled to an input voltage node and a system voltage node, and configured to obtain an input voltage of a power converter circuit and a system voltage of the power converter circuit, configured to obtain a voltage rate gain based on an aggregate inductance of the power converter circuit, and configured to, in accordance with a determination that the input voltage and the system voltage are not equal, generate a rate offset voltage based on the voltage rate gain and the system voltage difference.


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