The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Dec. 17, 2020
Applicant:

Adrc. Co. KR, Seoul, KR;

Inventors:

Duk Young Jeong, Seoul, KR;

Chae Yeon Hwang, Seoul, KR;

Dong Gyu Eo, Seoul, KR;

Assignee:

ADRC. CO. KR, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 29/00 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1251 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 27/1237 (2013.01); H01L 27/1288 (2013.01); H01L 29/24 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78675 (2013.01); H01L 29/78696 (2013.01);
Abstract

A thin film transistor panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate and including a first semiconductor layer including a low temperature polysilicon and a first control electrode overlapping the first semiconductor layer; a second transistor disposed on the substrate and including a second semiconductor layer including an oxide semiconductor and a second control electrode overlapping the second semiconductor layer; a first gate insulation layer disposed between the first semiconductor layer and the first control electrode of the first transistor and including a first insulation layer and a second insulation layer; and a second gate insulation layer disposed between the second semiconductor layer and the second control electrode of the second transistor and including the second insulation layer, wherein the density of the first insulation layer may be higher than the density of the second insulation layer, the first semiconductor layer of the first transistor may be in contact with the first insulation layer, and the second semiconductor layer of the second transistor may be in contact with the second insulation layer.


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