The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Apr. 20, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hwi-Chan Jun, Yongin-si, KR;

Seul-Ki Hong, Seoul, KR;

Hyun-Soo Kim, Hwaseong-si, KR;

Sang-Hyun Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 27/0886 (2013.01); H01L 29/41791 (2013.01); H01L 29/4232 (2013.01);
Abstract

A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.


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