logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11615857 B1

PDFFull Text
Date of Patent:
Mar. 28, 2023

Filed:

Apr. 06, 2021

Method for writing in a non-volatile memory according to the ageing of the memory cells and corresponding integrated circuit

Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Francesco La Rosa, Rousset, FR;

Enrico Castaldo, Catania, IT;

Francesca Grande, Syracuse, IT;

Santi Nunzio Antonino Pagano, Catania, IT;

Giuseppe Nastasi, San Filippo del Mela, IT;

Franco Italiano, San Filippo del Mela, IT;

Assignees:

STMICROELECTRONICS S.r.l., Agrate Brianza, IT;

STMICROELECTRONICS (ROUSSET) SAS, Rousset, FR;

Attorney:

Seed Intellectual Property Law Group LLP

Primary Examiner:

Thong Q Le

Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 27/11529 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/349 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 27/11529 (2013.01); G11C 16/0483 (2013.01);
Abstract

A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.

Find Patent Forward Citations

La Rosa, Francesco. (2023). Method for writing in a non-volatile memory according to the ageing of the memory cells and corresponding integrated circuit (U.S. Patent No. 11615857). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11615857

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…