The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Mar. 29, 2021
Applicant:

Phison Electronics Corp., Miaoli, TW;

Inventors:

Yu-Siang Yang, New Taipei, TW;

Wei Lin, Taipei, TW;

An-Cheng Liu, Taipei, TW;

Yu-Heng Liu, Hsinchu County, TW;

Chun-Hsi Lai, Hsinchu County, TW;

Ting-Chien Zhan, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 16/10 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/08 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 11/5671 (2013.01);
Abstract

A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.


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