The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Mar. 10, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Atsushi Kawasumi, Fujisawa Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); G06N 3/063 (2006.01); G06F 7/544 (2006.01); G06N 3/08 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G06F 7/5443 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G11C 5/06 (2013.01); G11C 11/4097 (2013.01);
Abstract

A semiconductor storage device has a plurality of memory cells that are arranged in a first direction and store first data, a plurality of first wiring pairs that are provided corresponding to the plurality of memory cells arranged in the first direction, and supply second data multiplied with the first data, a second wiring pair that is provided corresponding to two memory cells adjacent to each other in the first direction, and outputs multiplication data obtained by multiplying the first data stored in the two memory cells with the corresponding second data on the first wiring pair, and a third wiring pair in which potentials are changed depending on an addition result only when the addition result obtained by adding two multiplication data output to the second wiring pair to each other is not zero.


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