The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Dec. 28, 2018
Applicant:

Graphcore Limited, Bristol, GB;

Inventors:

Ola Tørudbakken, Oslo, NO;

Brian Manula, Stockholm, SE;

Harald Høeg, Oslo, NO;

Assignee:

Graphcore Limited, Bristol, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 12/0813 (2016.01); G06F 12/0868 (2016.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); H04L 12/54 (2022.01); H04L 12/70 (2013.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 9/3851 (2013.01); G06F 9/5027 (2013.01); G06F 12/0813 (2013.01); G06F 12/0868 (2013.01); G06F 13/1689 (2013.01); H04L 12/5601 (2013.01); H04L 2012/5618 (2013.01); H04L 2012/5625 (2013.01);
Abstract

A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having: an accelerator interface for connection to the subsystem to enable transfer of batches of data between the subsystem and the gateway; a data connection interface for connection to external storage for exchanging data between the gateway and storage; a gateway interface for connection to at least one second gateway; a memory interface connected to a local memory associated with the gateway; and a streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data are selectively via at least one of the accelerator interface, data connection interface, gateway interface and memory interface.


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