The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Aug. 05, 2019
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Liping Guo, Palo Alto, CA (US);

Yingdong Li, Palo Alto, CA (US);

Scott Furey, Cupertino, CA (US);

Salil Suri, Fremont, CA (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G11C 29/02 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 11/073 (2013.01); G06F 11/108 (2013.01); G11C 29/023 (2013.01); G11C 29/52 (2013.01);
Abstract

A NVM switch has been designed that allows multiple hosts to simultaneously and independently access a single port NVM device. While this active-active multi-host usage configuration allows for a variety of uses of lower cost single port NVM device, an issue with one of the hosts can delay or block transactions between the other host and the NVM device. The NVM switch includes logic that isolates activity of the multiple hosts despite logic of the switch being shared across the hosts. When the switch detects an issue with one host ('error host'), the switch clears the in-flight commands of the error host and flushes data of the error host. Likewise, the NVM switch ensure proper communication of error reporting from attached NVM devices to the multiple hosts.


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