The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Mar. 30, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Amrit Panda, Redmond, WA (US);

Francisco Perez, San Diego, CA (US);

Karamvir Chatha, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/32 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06F 9/325 (2013.01); G06F 9/30065 (2013.01); G06F 9/3877 (2013.01); G06N 3/063 (2013.01);
Abstract

An apparatus for hardware acceleration for use in operating a computational network is configured for determining that a loop structure including one or more loops is to be executed by a first processor. Each of the one or more loops includes a set of operations. The loop structure may be configured as a nested loop, a cascaded or a combination of the two. A second processor may be configured to decouple overhead operations of the loop structure from compute operations of the loop structure. The apparatus accelerates processing of the loop structure by simultaneously processing the overhead operations using the second processor separately from processing the compute operations based on the configuration to operate the computational network.


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