The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Mar. 22, 2021
Applicant:

Tata Consultancy Services Limited, Mumbai, IN;

Inventors:

Dhaval Shah, Thane West, IN;

Sunil Puranik, Pune, IN;

Manoj Nambiar, Thane West, IN;

Mahesh Damodar Barve, Pune, IN;

Ishtiyaque Shaikh, Thane West, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 69/12 (2022.01); H04L 49/9057 (2022.01); H04L 69/166 (2022.01);
U.S. Cl.
CPC ...
H04L 69/12 (2013.01); H04L 49/9057 (2013.01); H04L 69/166 (2013.01);
Abstract

A method and system of a re-assembly middleware in FPGA for processing TCP segments into application layer messages is disclosed. In recent years, the communication speed in digital systems has increased drastically and thus has brought in a growing need to ensure a good/high performance from the FPGA services. The disclosure proposes a re-assembly middleware in the FPGA for processing TCP segments into application layer messages at a pre-defined frequency for a good/high performance. The pre-defined frequency is a high frequency performance feature of the re-assembly middleware, wherein the FPGA's implementation frequency is at atleast 300 MHz based on a memory optimization technique. The memory optimization technique includes several strategies such registering an output and slicing memories.


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