The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Jun. 14, 2017
Applicants:

University of Florida Research Foundation, Inc., Gainesville, FL (US);

The University of Connecticut, Farmington, CT (US);

Inventors:

Mark M. Tehranipoor, Gainesville, FL (US);

Domenic J. Forte, Gainesville, FL (US);

Ujjwal Guin, Auburn, AL (US);

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 9/08 (2006.01); H04L 9/14 (2006.01); G09C 1/00 (2006.01); H04L 9/16 (2006.01); H04L 9/06 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
H04L 9/0825 (2013.01); G09C 1/00 (2013.01); H04L 9/0656 (2013.01); H04L 9/0662 (2013.01); H04L 9/08 (2013.01); H04L 9/14 (2013.01); H04L 9/16 (2013.01); H04L 9/3236 (2013.01); H04L 9/3247 (2013.01); H04L 2209/127 (2013.01); H04L 2209/26 (2013.01);
Abstract

Methods and integrated circuit architectures for assuring the protection of intellectual property between third party IP providers, system designers (e.g., SoC designers), fabrication entities, and assembly entities are provided. Novel design flows for the prevention of IP overuse, IP piracy, and IC overproduction are also provided. A comprehensive framework for forward trust between 3PIP vendors, SoC design houses, fabrication entities, and assembly entities can be achieved, and the unwanted modification of IP can be prevented.


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