The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Oct. 29, 2019
Applicant:

Excelitas Canada, Inc., Vaudreuil-Dorion, CA;

Inventors:

Gabriel Charlebois, Vaudreuil-Dorion, CA;

JinHan Ju, Kirkland, CA;

Lawrence Godfrey, Nanaimo, CA;

Assignee:

Excelitas Canada, Inc., Vaudreuil-Dorion, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/042 (2006.01); H05K 1/18 (2006.01); H05K 3/30 (2006.01); H01L 23/48 (2006.01); H01L 23/495 (2006.01); H03K 17/687 (2006.01); H05K 1/11 (2006.01); H05K 1/16 (2006.01); H05K 7/20 (2006.01); H01S 5/0231 (2021.01); H01S 5/02234 (2021.01); H01S 5/02325 (2021.01); H01S 5/02345 (2021.01); H01S 5/40 (2006.01);
U.S. Cl.
CPC ...
H01S 5/042 (2013.01); H01L 23/481 (2013.01); H01L 23/49589 (2013.01); H01S 5/0231 (2021.01); H01S 5/02234 (2021.01); H01S 5/02325 (2021.01); H01S 5/02345 (2021.01); H03K 17/687 (2013.01); H05K 1/115 (2013.01); H05K 1/162 (2013.01); H05K 1/181 (2013.01); H05K 3/303 (2013.01); H05K 7/2039 (2013.01); H01S 5/40 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10121 (2013.01); H05K 2201/10166 (2013.01); H05K 2201/10636 (2013.01); H05K 2201/10719 (2013.01);
Abstract

A surface mountable laser driver circuit package is configured to mount on a host printed circuit board (PCB). A surface mount circuit package includes a lead-frame. A plurality of laser driver circuit components is mounted on and in electrical communication with the lead-frame of the surface mount circuit package. A dielectric layer is located between the lead-frame and the host PCB and includes portals through the dielectric layer each arranged to accommodate an electrical connection between the lead-frame and the host PCB. The lead-frame and the dielectric layer are arranged such that a first lead-frame portion and a first dielectric layer portal align with a first end of a host PCB trace configured to provide a current return path for the surface mount laser driver, and a second lead-frame portion and a second dielectric layer portal align with a second end of the host PCB trace.


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