The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Feb. 18, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Tomoya Inden, Yokkaichi Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/105 (2006.01); H01L 27/11524 (2017.01); H01L 27/102 (2023.01); H01L 27/11551 (2017.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); H01L 27/1025 (2013.01); G11C 16/08 (2013.01); H01L 27/11551 (2013.01);
Abstract

A semiconductor memory device includes a substrate, first conductor layers, second conductor layers, a third conductor layer, and an insulator layer. The substrate includes a first region, a second region, and a third region separating the first and second regions. The first conductor layers are above the first region. The second conductor layers are above an uppermost one of the first conductor layers. The third conductor layer is above the second region. The insulator layer is above the second and third regions. The insulator layer includes first and second portions. The first portion is above the third conductor layer at a height from the substrate greater than a height of the uppermost one of the first conductor layers and extends along a substrate surface direction. The second portion extends along a substrate thickness direction and contacts a surface of the substrate in the third region.


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